The present invention relates generally to electronic devices, and more particularly to passive electronic devices.
U.S. Patent Application Publication No. 2003/0186453 describes nanocalorimeter arrays with thermal isolation regions on a substrate. A thermal isolation layer can include a plastic material in thin foil form ranging from less than 15 μm to approximately 25 μm in thickness, possibly as thin as 2 μm and as thick as 500 μm. Thermal equilibrium regions contain resistive thermometers, drop merging electrodes, and insulating layers deposited using standard fabrication techniques, such as lithographic patterning of thin films, microelectronic fabrication techniques (e.g. including sputtering, chemical etching, evaporation), and printed circuit board fabrication techniques. If amorphous silicon thermometer material is deposited, such as at temperatures in the range of 170-250° C., a substrate polymer film should have a high softening temperature. Deposition of vanadium oxide thermometer material can be done at a substantially lower temperature, allowing a substrate polymer with a lower softening point.
U.S. Patent Application Publication 2003/0134516 describes fabrication of an array of electronic devices such as a display or sensor. A droplet source ejects droplets of a masking material for deposit on a thin film or substrate surface to mask an element of an array. The droplets rapidly freeze upon contact and the thin film or substrate is then etched. A pixel of a large display system can include a thin-film transistor (TFT) or sensor or other emissive element. For example, a gate and ground plate can be formed in a first metal layer by depositing a phase change mask and then etching. A TFT's active region can be deposited, followed by a second metal layer in which a source, a data line, and a drain can be formed, again by depositing a phase change mask and etching. The drain, a dielectric, and the ground plate together can form a storage capacitor.
U.S. Patent Application Publication 2005/0136358 describes liftoff operations that involve printing liftoff patterns, such as multi-layer liftoff patterns. A mask structure may be formed from a liftoff operation, and can then be used as an etch mask, for example. The publication also describes printing of integrated circuit (IC) patterns directly on a substrate rather than using photolithography; a printed IC pattern may include gates and source and drain regions of thin film transistors, signal lines, opto-electronic device components, and so forth. Also, a patterned liftoff layer can include contact pads for an IC, electrodes for a transistor device or another structure or device, or bus lines.
It would be advantageous to have improved techniques for passive electronic devices.